Damage to integrated circuits through electrostatic discharge is a well known problem. The voltage in a discharge can easily reach a value of thousands of volts, while the damage threshold of devices within a circuit may be about 10 volts.
Conventionally, PN junctions are connected in parallel with the input/output terminals of the circuit, with a series resistance in the path of the signals to slow down the rise time of the electrostatic discharge (ESD) voltage.
U.S. Pat. No. 5,357,397 suggests etching the metal interconnection layers to form a pair of metal points that can serve to initiate a field emission discharge. This approach suffers from a lack of repeatability because of the etching technique chosen.